NAND memory arrays use high voltage switching transistors to isolate the erase voltage from the array and from sense amplifiers. Although both read and program operations use relatively low voltages, an erase operation couples a high magnitude voltage to the array. Thus high voltage switching transistors electrically decouple the array from the sensing circuits to avoid junction breakdown.
Commonly, during the erase operation of a 2D NAND memory array, the potential is raised in the PWI region, the uppermost p-type region in a triple well. One typical 2D NAND memory array arrangement uses a group of 4 high voltage switching MOSFETs positioned outside of the PWI region to electrically decouple the array from the erase voltage.
In another 2D NAND memory array arrangement the PWI region is shared by the memory array and the 4 switching MOSFETs to prevent large voltage differences and allow the use of low voltage design rules for the 4 switching MOSFETs. This latter arrangement adds a high voltage MOSFET outside of the PWI region, reducing the number of high voltage MOSFETS from 4 to 1 and thereby reducing the total area, despite the additional transistor.
3D NAND memory architecture also benefits from high voltage switching transistors to protect sensing circuits from the high magnitude erase voltage. However, 3D NAND memory can lack the PWI region, which in 2D NAND memory architecture can reduce the area consumed by high voltage switching circuitry.
As a result, in 3D NAND memory architecture, the high voltage switching transistors lines consume a significant amount of area. In an example memory array with 8 bit lines, and 2 planar switching transistors per bit line, 16 planar switching transistors are required to electrically couple the bit lines to erase voltage lines or to program and read voltage lines.
It would be desirable to reduce the area consumed by switching transistors for a 3D NAND memory array.